When multiple cores execute LDXR/STXR based atomic increments on the same cache line, observed latency shows a heavy tail that appears only under contention. The goal is to characterize the retry behavior of the exclusive monitor and quantify the resulting latency distribution for a specific implementation (e.g., Cortex‑A53) while varying the number of contending threads. What is the average number of LDXR/STXR retries per successful operation when two, four, and eight cores contend for the same line? How does the latency tail (e.g., 99th percentile) scale with thread count on this core? Are there measurable differences in EXCLUSIVE_ACCESS_FAIL counters that correlate with the observed latency spikes?

LDXR/STXR latency under concurrent aarch64 requests

Latency spikes in LDXR/STXR atomic loops under concurrent aarch64 core requests

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When multiple cores execute LDXR/STXR based atomic increments on the same cache line, observed latency shows a heavy tail that appears only under contention.

The goal is to characterize the retry behavior of the exclusive monitor and quantify the resulting latency distribution for a specific implementation (e.g., Cortex‑A53) while varying the number of contending threads.

What is the average number of LDXR/STXR retries per successful operation when two, four, and eight cores contend for the same line?
How does the latency tail (e.g., 99th percentile) scale with thread count on this core?
Are there measurable differences in EXCLUSIVE_ACCESS_FAIL counters that correlate with the observed latency spikes?

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Latency spikes in LDXR/STXR atomic loops under concurrent aarch64 core requests

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