aarch64 Memory Model: LDAR/STLR Visibility Limits Under Concurrent Access

Synchronization Constraints in Weakly Ordered Memory

The ARMv8-A architecture utilizes a weakly ordered memory model where hardware may reorder memory accesses to maximize throughput. To manage synchronization, the architecture provides Load-Acquire (LDAR) and Store-Release (STLR) instructions, which establish one-way barriers to ensure specific ordering between threads.

While these instructions provide a more performant alternative to full system barriers (DMB SY), there is a design uncertainty regarding the visibility of updates across multiple observers when concurrent requests access shared data. Specifically, while a store-release ensures prior accesses are visible before the release itself, the exact timing of visibility across different cores in a high-concurrency environment remains a critical consideration for low-latency design.

What are the specific limits of LDAR/STLR when multiple observers are concurrently polling a synchronization variable? Does the architecture guarantee a consistent observation order across all cores without an additional full barrier?