Does a store-release followed by a load-acquire guarantee visibility of pagination offsets on AArch64 without extra barriers?

Goal

Ensure that a consumer thread observing a readiness flag via a load-acquire also sees the pagination offset updated by a preceding store-release, preventing duplicate or skipped pages when bounding queries and paginating large datasets on AArch64.

Constraints and uncertainty

AArch64 follows a weak memory model where normal loads and stores may be reordered unless explicit barrier instructions (DSB, DMB, ISH) or matching acquire-release pairs are used. It is unclear whether the release-acquire pairing alone guarantees visibility of the offset, or whether additional memory barriers are required when the offset and flag reside in normal memory, and whether the result varies with memory type (device vs normal) or cacheability attributes.

• Does the release-acquire pairing alone prevent a consumer from observing a stale offset after seeing the flag?
• Are any additional DMB/DSB barriers required when the offset and flag are in normal memory?
• Does the outcome depend on whether the memory is marked as device or normal, or on cacheability attributes?