Instruction-cache invalidation for AArch64 self-modifying code after DC CVAC
Instruction-cache invalidation for AArch64 self-modifying code after DC CVAC The goal is to determine whether an AArch64 JIT or runtime that writes executable memory can rely on DC CVAC to the Point of Coherency plus a Data Synchronization Barrier alone, or whether an explicit instruction-cache invalidation and Instruction Synchronization Barrier are require