Mitigating Glitches in Synchronous Designs: A Task Guide

Desired Outcome

Mitigate glitch-induced timing violations and meta-stability in synchronous designs by synchronizing signal transitions to clock edges and validating operation with static timing analysis.

Necessary Prerequisites

• Familiarity with clock domain crossing (CDC) concepts
• Access to a synthesis tool and static timing analysis (STA) executable
• Design files in a standard format (e.g., Verilog or VHDL) with associated SDC constraints

Focused Procedure

1. Identify glitch sources in combinational logic crossing clock domains. Use simulation or formal analysis to locate transient transitions.

2. Insert pipeline registers to break long combinational paths, ensuring transitions synchronize to clock edges. A two-stage synchronizer flop pair is standard for clock domain crossing.

   verilog
   module synchronizer (
     input async_signal,
     input clk,
     output synchronized_signal
   );
     reg [1:0] stage;
     always @(posedge clk) begin
       stage <= {stage[0], async_signal};
     end
     assign synchronized_signal = stage[1];
   endmodule

3. Apply double-clock gating to suppress glitches in clock paths. A gating register ANDed with the clock signal can disable the clock during unwanted transitions, reducing glitch propagation.

   Configuration example: clk & gating_register where the gating register toggles based on valid data conditions.

4. Run static timing analysis with the updated netlist. Use the opensta executable as an example:

   bash
   opensta design.sdc
   report_timing -setup -hold

   Run from a shell with read access to the design and SDC files. Meaningful placeholders: design_name, sdc_file. Expected checks: setup slack must be < clock period minus setup time; hold slack must be positive. Relevant risks: incorrect SDC constraints may report false violations; added gating registers increase dynamic power and area.

5. Compare timing reports with and without glitch-mitigation cells to verify improvement. Synthesize a small testbench and run STA to compare setup/hold compliance.

Expected Checks

• Setup slack: must be within acceptable margins; glitches often reduce setup margin.
• Hold slack: must be positive; glitches can cause hold violations near clock edges.
• Meta-stability metrics: mean time between failures (MTBF) if synchronizers are present, verified via formal analysis.

Relevant Recovery Options

• If timing violations persist, rebalance logic or increase clock period to absorb slack.
• Reset the synchronizer domain using an asynchronous reset with proper de-assertion timing to avoid metastable propagation.
• Document area and dynamic power trade-offs of added registers against reliability gains for the target process node.