India’s semiconductor push: funds, fab plans and design progress

India’s semiconductor push in late 2026: funding, fab plans and design progress

In September 2026, India’s semiconductor strategy moved from policy talks to concrete investments, as highlighted by the Semicon India 2026 event and statements from Union Minister Ashwini Vaishnaw. The government’s second phase of the semiconductor programme earmarks ₹1.27 lakh crore to broaden the domestic ecosystem and lure global players.

Government funding and policy

Under the Semicon 2.0 scheme, the state has pledged around ₹1.27 lakh crore (about $13.5 billion) to build capabilities across design, fabrication, equipment and materials. Minister Vaishnaw said the aim is to move beyond chip assembly and testing, targeting end‑use products such as automotive electronics, power‑system chips and household appliances. He cited a display‑control module plant planned in Uttar Pradesh and an LED‑display fab by Crystal Matrix that has reduced feature size from 90 µm to 40 µm as early signs of this ambition.

Corporate commitments and fab aspirations

At the Semicon India 2026 exhibition, Applied Materials announced a $5 billion (~₹48,000 crore) investment over the next decade, while Lam Research pledged ₹10,000 crore for a silicon‑component facility in India. ASML set up an office in the country and projected that by 2032 India could host 15‑25 % of its local wafer‑fab demand, implying the need for several new fabs. Tata Electronics signed 16 vendor agreements to support its ₹1.18 lakh crore chip‑manufacturing unit in Dholera, Gujarat, and a chip‑assembly‑test site in Assam, and is developing a 363‑acre vendor park to house about 450 suppliers.

Fabrication realities and gaps

The only government‑owned fab, the Semi‑Conductor Laboratory (SCL), is receiving ₹4,500 crore for a three‑fold capacity increase, but its technology remains limited to 180 nm nodes—far behind the advanced nodes needed for AI and high‑performance computing. As noted in The Ken, the promised 100‑times capacity jump and a shift to 28 nm chips has not materialised; instead, SCL’s upgrade strengthens its existing role in serving agencies and student prototyping.

Design‑linked progress

The design‑linked incentive scheme has backed 24 chip‑design startups, extended EDA tool access to more than 100 firms and produced 23 tapeouts. Notable among them is Netra Semiconductor’s A2000 AI processor, taped out on TSMC’s 12 nm node, showing that Indian design houses can achieve advanced results even while domestic fab capacity lags.

Overall, India’s semiconductor push combines large‑scale fiscal incentives and corporate pledges with measurable design achievements, while acknowledging that closing the fab‑technology gap will take years.