TLBI configuration for ASID-scoped invalidation with variable page granule

Designing TLB maintenance for ARMv8-A aarch64 with multi-level page tables and ASID support.

The goal is to define a consistent invalidation policy that respects the page granule size selected in TCR_ELx and ASID allocation across cores. The architecture provides TLBI instructions with variants for VA, VA range, ASID-specific and broadcast behavior. Uncertainty remains about which instruction variants guarantee broadcast to all cores for a given granule size and ASID scope, and how ASID allocation interacts with context switch overhead when multiple granules are supported.

Broadcast semantics for TLBI may vary by implementation and instruction variant and require current verification against the ARM Architecture Reference Manual for the targeted profile. Practical verification would involve inspection of TCR_ELx values and architectural simulation.

• What instruction variant provides ASID-scoped invalidation that is guaranteed to broadcast across cores for 16KB and 64KB granules?
• Under what TCR_ELx configuration does ASID tagging apply to Stage 1 translations?
• What permission boundary limits software visibility of broadcast completion for TLBI operations?