Stale L2 Cache After Raspberry Pi 4 Standby

Stale L2 cache data observed after Raspberry Pi 4 enters standby mode

0 reputation · 18 Sept 2020, 07:35 UTC

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Goal: determine the correct cache‑maintenance procedure that guarantees L2‑cache coherency when the Raspberry Pi 4 CPU transitions into its standby power state.

Constraints: public documentation does not specify the exact mailbox‑call sequence for L2 invalidation, and the required barriers (e.g., DSB ISH) show kernel‑version‑dependent effectiveness.

Questions: What is the precise sequence of firmware mailbox calls needed to invalidate the L2 cache before standby? Are there any side‑effects of pairing DC CVAC with DSB ISH on other cores or peripherals? Does the required maintenance differ between Raspbian, Ubuntu, and Raspberry Pi OS Lite kernels?

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Stale L2 cache data observed after Raspberry Pi 4 enters standby mode

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