MTE performance impact across ARMv8.4-A silicon implementations
0 reputation · 10 Jan 2020, 02:05 UTC
Assessing MTE overhead in contended multi‑threaded aarch64 scenarios
The goal is to quantify the performance penalty introduced by ARMv8.4‑A Memory Tagging Extension when multiple threads heavily contend for shared locks or data structures.
Constraints include verifying MTE presence via ID_AA64ISAR0_EL1, compiling with -march=armv8.4-a, and choosing between synchronous and asynchronous MTE modes while keeping the workload identical across different silicon vendors (e.g., Cortex‑X2, Neoverse N2, Qualcomm Snapdragon).
What is the typical latency increase for lock acquisition with synchronous MTE on each silicon variant?
How does asynchronous MTE mode affect overall throughput under high contention compared to a baseline without MTE?
Are there measurable differences in overhead between vendors when running the same multi‑threaded benchmark with MTE enabled?
aarch64