High cycle count with low IPC observed via perf stat

When investigating a suspected CPU performance issue, the first step is to run perf stat on the workload and look for a high cycle count coupled with a low instructions‑per‑cycle (IPC) ratio, which suggests the processor is spending many cycles without retiring instructions.

The goal is to determine whether this pattern truly reflects a CPU bottleneck or is influenced by measurement artifacts such as sampling frequency choice, counter multiplexing, or restricted access to hardware counters.

Uncertainty remains around selecting an appropriate perf record sampling frequency that captures short‑lived hotspots without adding noticeable overhead, how to interpret results when the PMU must multiplex requested events, and whether the current perf_event_paranoid setting allows collection of the needed counters in the target environment (bare metal, VM, or container).

• What sampling frequency balances accuracy and overhead for detecting short hotspots?
• How can counter multiplexing effects be accounted for when comparing perf stat outputs across different runs?
• Does the existing perf_event_paranoid value permit the required hardware‑counter collection on this system?