GIC v3 Interrupt Affinity Routing and SMC Secure Monitor Call Interoperability on aarch64

Determine how to ensure consistent interrupt handling between GIC v3 affinity routing and SMC secure call interfaces across different aarch64 platforms.

GIC affinity is platform‑specific and depends on kernel device‑tree settings, while SMC/HVC behavior varies with firmware implementations such as UEFI, OP‑TEE, or coreboot and with kernel version.

How can the kernel enforce a unified interrupt routing policy that aligns with SMC call expectations across heterogeneous firmware? What device‑tree or kernel configuration knobs are required to guarantee that GIC v3 affinity masks match the CPU interface used by SMC? Is there a documented method to synchronize periodic timer state with SMC secure world entry/exit on aarch64?