DC CVAC's Point of Coherency Scope in ARMv8.2: Stale Cache Uncertainty

Goal

Determine whether the DC CVAC instruction alone guarantees visibility of data written on one core to all other cores on ARMv8.2 systems, given the implementation‑defined shareability of its point of coherency (PoC).

Constraints & Uncertainty

The ARMv8‑A manual specifies that PoC may be either inner‑shareable or outer‑shareable, with no architectural change across ARMv8.0‑v8.2. This ambiguity can lead to stale cache observations when a core writes to a location that is only outer‑shareable cached on another core, without additional cache maintenance or synchronization.

Questions

• Is the PoC for DC CVAC guaranteed to be outer‑shareable on all ARMv8.2 implementations?
• Under what conditions does DC CVAC fail to propagate writes to other cores, leading to stale data?
• Should developers default to DC CIVAC or add explicit DSB SY barriers after DC CVAC for correct inter‑core synchronization?