Implementing Parallel Regions in an SDL State Machine: A Step‑by‑Step Guide

Desired Outcome

By the end of this guide you will have a working SDL state machine that uses parallel regions to model two independent sub‑states that can be active simultaneously. You will be able to simulate the model, check for deadlocks, and verify that transitions target the correct region.

Prerequisites

• Commercial SDL modeling tool installed (e.g., SDL Studio 3.2.2, SCADE System 5.3, or equivalent). The tool must support the parallel keyword and integrated model‑checking.
• Basic knowledge of SDL syntax: states, transitions, events, and actions.
• Administrative access to create and modify projects on the machine.
• Optional: a test harness or external system to generate events for simulation.

Step‑by‑Step Construction

1. Create a New Project
   • Launch the SDL tool and select New Project → State Machine.
   • Name the project ParallelDemo and choose a location on disk.
   • Verify that the project is set to SDL version 3.2.2 or later.
2. Define the Parent State
   • Create a state named Processing in the main state machine.
   • In the state properties, check the box labeled Parallel (or add the keyword parallel in the advanced text editor).
   • Set the initial state of Processing to Start (the default).
3. Add Nested States (Regions)
   • Within Processing, add two child states: Input and Output. Each of these becomes a parallel region.
   • Give each region a unique name and add entry/exit actions. Example:

     state Input
       entry: log("Input entered")
       exit: log("Input exited")
     end
     
     state Output
       entry: log("Output entered")
       exit: log("Output exited")
     end

4. Define Transitions Within Regions
   • In Input, add a transition on event data_ready to a sub‑state ProcessData.

     state ProcessData
       entry: log("Processing data")
     end
     
     transition Input.process_data
       event: data_ready
       target: ProcessData
     end

   • In Output, add a transition on event send_complete to a sub‑state SendAck.

     state SendAck
       entry: log("Sending acknowledgment")
     end
     
     transition Output.send_ack
       event: send_complete
       target: SendAck
     end

5. Transitions Between Regions (Optional)
   • To coordinate between regions, use a wildcard transition that targets both. Example: a global event reset that brings both regions back to their initial sub‑state.

     transition Processing.reset
       event: reset
       target: Input.Start, Output.Start
     end

6. Validate Syntax and Names
   • Run the tool’s syntax checker. Confirm that region names Input and Output are unique within Processing.
   • Check that all transitions explicitly reference a region or use a wildcard. Ambiguous targets are flagged as errors.
7. Simulate the Model
   • Start the simulation engine from the tool’s toolbar.
   • Send events manually or via the test harness: data_ready, send_complete, reset.
   • Observe the state diagram: both ProcessData and SendAck should be active concurrently when their events occur.
   • Use the State History view to verify that transitions are evaluated independently.
8. Run Model‑Checking
   • Open the Model‑Check panel and select the property set: No Deadlock, Event Propagation.
   • Execute the check. The report should list no violations if transitions are correctly scoped.
   • Review any warnings about unreachable states or missing exit conditions.
9. Recover from Common Issues
   • Ambiguous Transition Target: If the checker flags a transition, ensure you prefix the target with the region name, e.g., Input.ProcessData.
   • Unintended Wildcard Capture: If a wildcard transition consumes events meant for a specific region, replace it with a region‑specific transition.
   • Missing Exit Condition: If a region has no exit state, the simulation may hang. Add an explicit Exit state or a transition that brings the region back to its initial state.
   • Deadlock Reported: Verify that all parallel regions have at least one exit path. If a region can become stuck, introduce a timeout transition or a global reset.
10. Export and Deploy
    • Once verified, export the model as a target‑specific code file (e.g., C, Ada) using the tool’s code generator.
    • Integrate the generated module into your system, ensuring that the event dispatching layer sends the correct SDL events.

Expected Checks and Verification

• Simulation Log: Confirm that entry and exit actions fire for both regions independently.
• State Diagram: At any simulation step, the diagram should show two active leaf states under Processing.
• Model‑Check Report: No deadlock or unreachable state warnings. If any appear, follow the recovery steps above.
• Runtime Monitoring: In a deployed system, use a watchdog to detect if either region remains in a non‑terminal state beyond a threshold.

Practical Tips

• Keep region names short but descriptive to avoid confusion when referencing them in transitions.
• Use the tool’s Transition Editor to visually confirm that a transition’s source and target are correctly linked to the intended region.
• When adding new regions, immediately run a quick simulation to ensure the parent state’s parallel flag remains active.
• Document each region’s purpose in the model’s comments; this aids future maintenance.

Limitations and Caveats

• Parallel regions are only supported in SDL versions 3.0+; older tools will reject the parallel keyword.
• Model‑checking performance degrades with many regions and complex transitions; consider modularizing the state machine if you hit timeouts.
• Some commercial tools may require a separate license for the model‑checking feature.
• Runtime execution of parallel regions depends on the underlying code generator’s support for concurrency (e.g., multi‑threaded vs. cooperative scheduling).

Conclusion

Parallel regions provide a clean way to model concurrent behavior in SDL. By following this guide—defining unique regions, explicitly targeting transitions, and validating through simulation and model‑checking—you can build robust, deadlock‑free state machines that reflect real‑world concurrent processes.