Deploying a LabVIEW FPGA Moving‑Average Filter on NI CompactRIO

Problem: Getting Deterministic Filtering on CompactRIO

When you need sub‑microsecond latency for sensor data—such as high‑speed vibration monitoring or motor current sampling—a software loop running on the real‑time controller often introduces jitter. Offloading the filter to the FPGA on an NI‑RIO device gives deterministic execution, but the bitfile must be built, transferred, and verified correctly.

Solution Overview

LabVIEW’s FPGA Module lets you draw parallel hardware logic graphically. The FPGA VI is compiled into a .bitfile that the NI‑RIO driver downloads to the target CompactRIO chassis. Once loaded, the FPGA runs independently of the real‑time OS, providing fixed‑point arithmetic and pipeline‑style throughput.

Worked Example: Moving‑Average Filter

1. Create the FPGA VI
   • Open a LabVIEW project, add an FPGA target (e.g., NI cRIO‑904x).
   • Create a new FPGA VI and place an Analog Input node for the channel you want to filter.
   • Insert a Shift Register to hold the last N samples.
   • Use a For Loop (set to N iterations) to sum the shift register values and the new sample, then divide by N (use a fixed‑point Divide function).
   • Output the averaged value to an Analog Output node or a DMA FIFO for the real‑time VI.
2. Configure Clock and Resources
   • Set the FPGA clock to the device’s maximum (e.g., 40 MHz for many CompactRIO modules).
   • Open the FPGA VI’s Properties → Item Tab → FPGA Target to view the estimated resource usage (DSP slices, flip‑flops, LUTs).
3. Compile the Bitfile
   • Click the Run arrow; LabVIEW compiles the VI and produces MovingAverage_FPGA.bitfile in the project’s build folder.
4. Deploy to CompactRIO
   • Launch NI MAX, select your CompactRIO under Devices and Interfaces.
   • Go to the FPGA tab, click Download Bitfile, browse to the generated .bitfile, and confirm.
   • MAX will show a progress bar; if the download fails, check the firmware version (must match the LabVIEW FPGA Module version).
5. Run a Simple Test VI
   • Create a real‑time VI that writes a known DC voltage (e.g., 2.5 V) to the same analog input channel.
   • Read the filtered output via a DMA FIFO or Analog Output and verify that the value equals the input (within the filter’s quantization error).
   • Toggle a digital output line (e.g., LED) each time a new filtered sample is available to visually confirm activity.

Verification and Trade‑offs

After deployment, open the downloaded bitfile in NI MAX (FPGA → Properties) and compare the reported DSP slice and flip‑flop counts against the device’s specifications (e.g., a Xilinx Kintex‑7 on a cRIO‑904x provides ~200 DSP slices). If utilization exceeds 80 %, consider reducing the filter length N or using a cascaded integrator‑comb (CIC) structure to lower resource demand.

Latency can be checked with an oscilloscope: probe the raw analog input and the filtered output; the deterministic delay should equal the number of pipeline stages multiplied by the clock period (e.g., 3 stages × 25 ns = 75 ns at 40 MHz). Any measurable jitter indicates a problem with the bitfile download or an overloaded FPGA.

Limitation: Not all LabVIEW functions synthesize to FPGA. Avoid file I/O, complex string handling, or dynamic memory allocation inside the FPGA VI; these will cause compilation errors. Move such code to the real‑time controller and communicate via DMA FIFOs or shared variables.

Actionable Closing

To get reliable, low‑latency filtering on CompactRIO:

1. Keep the FPGA algorithm simple and resource‑light.
2. Always verify firmware compatibility in MAX before downloading a new bitfile.
3. Use the resource report and a quick I/O test (known input → expected output) as your acceptance criteria.
4. If the design grows beyond the device’s capacity, refactor the algorithm (e.g., halve the filter length or use pipelined multiplication) rather than trying to force a larger bitfile.

Following these steps gives you a deterministic filter that runs at the FPGA’s clock speed, freeing the real‑time loop for higher‑level control tasks.